1 piece Altera Stratix EP1S30F7800C7L, pulls,

Description: exact items shown - Stratix FPGA from network enterprise server. The Stratix Handbook, which covers these devices is here: https://www.mouser.com/datasheet/2/612/stratix_handbook-1299400.pdf You are buying one at a time, choose the quantity you want from the pull down list. I have see other folks reinstall BGA units after removal, I have not done that myself, please look at the photos, I did not clean these up after removal. if you don't think you can clean up the BGA or use a socket, please buy new ones and don't mess with these. note to me: top gray drawer in blue anti-satic bag Series:Stratix EP1S30Number of Logic Elements:32470 LEAdaptive Logic Modules - ALMs:-Embedded Memory:3.16 MbitNumber of I/Os:597 I/OSupply Voltage - Min:1.5 VSupply Voltage - Max:1.5 VMinimum Operating Temperature:0 CMaximum Operating Temperature:+ 70 CMounting Style:SMD/SMTPackage / Case:FBGA-780Packaging:TrayBrand:AlteraMaximum Operating Frequency:66 MHzMoisture Sensitive:YesNumber of Logic Array Blocks - LABs:3247 LABOperating Supply Current:114 mAOperating Supply Voltage:1.5 VProduct Type:FPGA - Field Programmable Gate Array From the Stratix Handbook S51002-3.2 2–2 Altera Corporation Stratix Device Handbook, Volume 1 July 2005 Functional Description : Stratix® devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks. The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318 MHz. M512 blocks are grouped into columns across the device in between certain LABs. M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 291 MHz. These blocks are grouped into columns across the device in between certain LABs. M-RAM blocks are true dual-port memory blocks with 512K bits plus parity (589,824 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 144-bits wide at up to 269 MHz. Several M-RAM blocks are located individually or in pairs within the device’s logic array. Digital signal processing (DSP) blocks can implement up to either eight full-precision 9 × 9-bit multipliers, four full-precision 18 × 18-bit multipliers, or one full-precision 36 × 36-bit multiplier with add or subtract features. These blocks also contain 18-bit input shift registers for digital signal processing applications, including FIR and infinite impulse response (IIR) filters. DSP blocks are grouped into two columns in each device. Each Stratix device I/O pin is fed by an I/O element (IOE) located at the end of LAB rows and columns around the periphery of the device. I/O pins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and six registers for registering input, output, and output-enable signals. When used with dedicated clocks, these registers provide exceptional performance and interface support with external memory devices such as DDR SDRAM, FCRAM, ZBT, and QDR SRAM devices. High-speed serial interface channels support transfers at up to 840 Mbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards.

Price: 35 USD

Location: Santa Monica, California

End Time: 2024-05-22T03:09:17.000Z

Shipping Cost: N/A USD