Ultra-Low Energy Domain-Specific Instruction-Set Processors by Francky Catthoor

Description: Ultra-Low Energy Domain-Specific Instruction-Set Processors by Francky Catthoor, Praveen Raghavan, Andy Lambrechts, Murali Jayapala, Angeliki Kritikakou, Javed Absar This book presents a systematic methodology for exploiting word-width information in embedded compilers. It details a technique for a context-driven strength reduction for constant multiplications, including a trade-off with application accuracy requirements. FORMAT Hardcover LANGUAGE English CONDITION Brand New Publisher Description Modern consumers carry many electronic devices, like a mobile phone, digital camera, GPS, PDA and an MP3 player. The functionality of each of these devices has gone through an important evolution over recent years, with a steep increase in both the number of features as in the quality of the services that they provide. However, providing the required compute power to support (an uncompromised combination of) all this functionality is highly non-trivial. Designing processors that meet the demanding requirements of future mobile devices requires the optimization of the embedded system in general and of the embedded processors in particular, as they should strike the correct balance between flexibility, energy efficiency and performance. In general, a designer will try to minimize the energy consumption (as far as needed) for a given performance, with a sufficient flexibility. However, achieving this goal is already complex when looking at the processor in isolation, but, in reality, the processor is a single component in a more complex system. In order to design such complex system successfully, critical decisions during the design of each individual component should take into account effect on the other parts, with a clear goal to move to a global Pareto optimum in the complete multi-dimensional exploration space.In the complex, global design of battery-operated embedded systems, the focus of Ultra-Low Energy Domain-Specific Instruction-Set Processors is on the energy-aware architecture exploration of domain-specific instruction-set processors and the co-optimization of the datapath architecture, foreground memory, and instruction memory organisation with a link to the required mapping techniques or compiler steps at the early stages of the design. By performing an extensive energy breakdown experiment for a complete embedded platform, both energy and performance bottlenecks have been identified, together with the important relations between thedifferent components. Based on this knowledge, architecture extensions are proposed for all the bottlenecks. Notes 1. General overview and context2. Global state-of-the-art overview3. Energy consumption breakdown for embedded platform targets4. High level embedded arch and compiler requirements5. Overall architecture exploration framework6. Clustered loop buffer and data cluster organisation7. Multi-threading in uni-threaded processors8. Indirectly addressed arrays and dynamic data structure handling on scratchpad memories9. Asymmetric foreground memory organisation10. Exploiting word-width information in the processor datapath11. Advanced strength reduction in shift-add based operations12. Bioimaging application demonstrator Back Cover Modern consumers carry many electronic devices, like a mobile phone, digital camera, GPS, PDA and an MP3 player. The functionality of each of these devices has gone through an important evolution over recent years, with a steep increase in both the number of features as in the quality of the services that they provide. However, providing the required compute power to support (an uncompromised combination of) all this functionality is highly non-trivial. Designing processors that meet the demanding requirements of future mobile devices requires the optimization of the embedded system in general and of the embedded processors in particular, as they should strike the correct balance between flexibility, energy efficiency and performance. In general, a designer will try to minimize the energy consumption (as far as needed) for a given performance, with a sufficient flexibility. However, achieving this goal is already complex when looking at the processor in isolation, but, in reality, the processor is a single component in a more complex system. In order to design such complex system successfully, critical decisions during the design of each individual component should take into account effect on the other parts, with a clear goal to move to a global Pareto optimum in the complete multi-dimensional exploration space. In the complex, global design of battery-operated embedded systems, the focus of Ultra-Low Energy Domain-Specific Instruction-Set Processors is on the energy-aware architecture exploration of domain-specific instruction-set processors and the co-optimization of the datapath architecture, foreground memory, and instruction memory organisation with a link to the required mapping techniques or compiler steps at the early stages of the design. By performing an extensive energy breakdown experiment for a complete embedded platform, both energy and performance bottlenecks have been identified, together with the important relations between the different components. Based on this knowledge, architecture extensions are proposed for all the bottlenecks. Author Biography Francky Catthoor is a leading researcher at IMEC and is very well established within the EDA community. He is IEEE Fellow and has edited and authored 6 books for Springer/Kluwer. Table of Contents Global State-of-the-Art Overview.- Energy Consumption Breakdown and Requirements for an Embedded Platform.- Overall Framework for Exploration.- Clustered L0 (Loop) Buffer Organization and Combination with Data Clusters.- Multi-threading in Uni-threaded Processor.- Handling Irregular Indexed Arrays and Dynamically Accessed Data on Scratchpad Memory Organisations.- An Asymmetrical Register File: The VWR.- Exploiting Word-Width Information During Mapping.- Strength Reduction of Multipliers.- Bioimaging ASIP benchmark study.- Conclusions. Long Description Modern consumers carry many electronic devices, like a mobile phone, digital camera, GPS, PDA and an MP3 player. The functionality of each of these devices has gone through an important evolution over recent years, with a steep increase in both the number of features as in the quality of the services that they provide. However, providing the required compute power to support (an uncompromised combination of) all this functionality is highly non-trivial. Designing processors that meet the demanding requirements of future mobile devices requires the optimization of the embedded system in general and of the embedded processors in particular, as they should strike the correct balance between flexibility, energy efficiency and performance. In general, a designer will try to minimize the energy consumption (as far as needed) for a given performance, with a sufficient flexibility. However, achieving this goal is already complex when looking at the processor in isolation, but, in reality, the processor is a single component in a more complex system. In order to design such complex system successfully, critical decisions during the design of each individual component should take into account effect on the other parts, with a clear goal to move to a global Pareto optimum in the complete multi-dimensional exploration space. In the complex, global design of battery-operated embedded systems, the focus of Ultra-Low Energy Domain-Specific Instruction-Set Processors is on the energy-aware architecture exploration of domain-specific instruction-set processors and the co-optimization of the datapath architecture, foreground memory, and instruction memory organisation with a link to the required mapping techniques or compiler steps at the early stages of the design. By performing an extensive energy breakdown experiment for a complete embedded platform, both energy and performance bottlenecks have been identified, together with the important relations between the different components. Based on this knowledge, architecture extensions are proposed for all the bottlenecks. Feature A systematic methodology for exploiting word-width information in embedded compilersSoftware method to enable heterogeneous data parallelism (SIMD)Technique for a context-driven strength reduction for constant multiplications, including a trade-off with application accuracy requirements Description for Sales People 1. General overview and context 2. Global state-of-the-art overview 3. Energy consumption breakdown for embedded platform targets 4. High level embedded arch and compiler requirements 5. Overall architecture exploration framework 6. Clustered loop buffer and data cluster organisation 7. Multi-threading in uni-threaded processors 8. Indirectly addressed arrays and dynamic data structure handling on scratchpad memories 9. Asymmetric foreground memory organisation 10. Exploiting word-width information in the processor datapath 11. Advanced strength reduction in shift-add based operations 12. Bioimaging application demonstrator Details ISBN9048195276 Author Javed Absar Short Title ULTRA-LOW ENERGY DOMAIN-SPECIF Language English ISBN-10 9048195276 ISBN-13 9789048195275 Media Book Format Hardcover Publisher Springer Series Embedded Systems Year 2010 Place of Publication Dordrecht Country of Publication Netherlands Imprint Springer Birth 1959 Pages 406 Edition 2010th DEWEY 621.391 Illustrations XXII, 406 p. DOI 10.1007/978-90-481-9528-2 Publication Date 2010-08-22 Edition Description 2010 ed. Alternative 9789400733060 Audience Professional & Vocational We've got this At The Nile, if you're looking for it, we've got it. With fast shipping, low prices, friendly service and well over a million items - you're bound to find what you want, at a price you'll love! TheNile_Item_ID:96261462;

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